module Add32 (
	input [31:0] a,
	input [31:0] b,
	input cin, 
	input clk,
	input cclr,
	output reg cout,
	output reg [31:0] sum
);

	wire [7:0] t_cout;
	wire [31:0] t_sum;

	CarryLookaheadAdder4 f0(
		.a(a[3:0]),
		.b(b[3:0]),
		.cin(cin),
		.clk(cin),
		.cclr(cclr),
		.sum(t_sum[3:0]),
		.cout(t_cout[0])
	);

	CarryLookaheadAdder4 f1(
		.a(a[7:4]),
		.b(b[7:4]),
		.cin(t_cout[0]),
        .clk(t_cout[0]),
		.cclr(cclr),
		.sum(t_sum[7:4]),
		.cout(t_cout[1])
	);

	CarryLookaheadAdder4 f2(
		.a(a[11:8]),
		.b(b[11:8]),
		.cin(t_cout[1]),
		.clk(t_cout[1]),
		.cclr(cclr),
		.sum(t_sum[11:8]),
		.cout(t_cout[2])
	);

	CarryLookaheadAdder4 f3(
		.a(a[15:12]),
		.b(b[15:12]),
		.cin(t_cout[2]),
		.clk(t_cout[2]),
		.cclr(cclr),
		.sum(t_sum[15:12]),
		.cout(t_cout[3])
	);

	CarryLookaheadAdder4 f4(
		.a(a[19:16]),
		.b(b[19:16]),
		.cin(t_cout[3]),
        .clk(t_cout[3]),
		.cclr(cclr),
		.sum(t_sum[19:16]),
		.cout(t_cout[4])
	);	
	
	CarryLookaheadAdder4 f5(
		.a(a[23:20]),
		.b(b[23:20]),
		.cin(t_cout[4]),
		.clk(t_cout[4]),
		.cclr(cclr),
		.sum(t_sum[23:20]),
		.cout(t_cout[5])
	);	
	
	CarryLookaheadAdder4 f6(
		.a(a[27:24]),
		.b(b[27:24]),
		.cin(t_cout[5]),
		.clk(t_cout[5]),
		.cclr(cclr),
		.sum(t_sum[27:24]),
		.cout(t_cout[6])
	);

	CarryLookaheadAdder4 f7(
		.a(a[31:28]),
		.b(b[31:28]),
		.cin(t_cout[6]),
		.clk(t_cout[6]),
		.cclr(cclr),
		.sum(t_sum[31:28]),
		.cout(t_cout[7])
	);

	always @(posedge clk or negedge cclr) begin
		if (!cclr) begin
			sum <= 0;
			cout <= 0;
		end
		else begin
			sum <= t_sum;
			cout = t_cout[7];
		end
	end
    
endmodule
